1. Field of the Invention
The invention relates to a semiconductor memory device having a widened contact area.
2. Description of the Background Art
A NAND flash memory is known as one of non-volatile semiconductor memories in which data can be electrically restored (EEPROM, Electrically Erasable and Programmable Read Only Memory) among semiconductor memory devices. In the NAND flash memory, a plurality of memory cells (2n memory cells, such as 32 memory cells, 64 memory cells, etc.) are connected in series to constitute a NAND memory cell unit (NAND string).
The NAND string has an element region in which source/drain diffusion layers are formed alternately so as to sandwich a channel region on a surface of a well layer formed on a semiconductor substrate. A side face of the element region along the NAND string is electrically separated by an element isolation region.
Select gate transistors (hereinafter referred to as select transistors) are arranged at both ends of the NAND string so as to selectively connect the NAND string to either a bit line or a source line. Each control gate of the memory cell in the NAND string is connected in a word line direction, and forms a word line. The gate of the select transistor is a portion of a select gate line in parallel with the word line. The bit line intersects with the word line at a right angle, and is arranged in parallel with the element region.
Since adjacent memory cells of the NAND string share a source/drain diffusion region, the NAND flash memory has a smaller unit cell size than other cell array types. Therefore, the NAND flash memory can have a large capacity. Further, the width of the element region, the width of the element separation region, the word line, and the like have been generally disposed by a line/space (hereinafter referred to as L/S) of the minimum processing size F (Feature Size).
The select transistors on both ends of the NAND string are required to suppress short channel effect and have controllability of threshold voltages. For example, even when the width of the element region and the word line is formed with the minimum processing size F, the select gate line generally has a wide width.
The bit line is connected with the element region formed with the width of the minimum processing size via a contact plug. As the capacity becomes larger, the minimum processing size F becomes smaller. As a result, the positional displacement relatively becomes larger, which makes it difficult to connect the element region and the contact plug. Even if there is no displacement, the contact area inevitably decreases, and there is a potential problem in that the contact resistance increases.
For example, Japanese Patent Application Laid-Open No. 1995-202143 discloses a semiconductor memory device in which the positions of contact plugs are alternately shifted in the bit line direction, namely, in a direction of a fringe region. In case of the contact plugs are arranged in a zigzag manner, the distance to the contact section of an adjacent element region can be ensured, and the breakdown voltage between the NAND strings can also be ensured. The bit line of the disclosed semiconductor memory device has a fringe at a connecting portion with the contact plug.
Since the disclosed contact plugs of the semiconductor memory device are arranged to be alternately shifted in the direction of the element region, a widened portion similarly to the bit line may be arranged at a contact area with the element region so that the contact area increases in order to suppress the increase of the contact resistance. In such case, however, it is necessary to space apart adjacent element regions by at least the distance equivalent to the widened width of the element regions. Therefore, there is a problem in that the element region other than the widened portion is formed larger than the minimum processing size F, and further, in case of the control gate (word line) and the select gate line are arranged in accordance with the zigzag of the contact plugs in order to improve the uniformity of the cell characteristics, there is no choice but to increase the distance between the control gates and the like.